A robust power distribution network both for chips and packages is one of the critical tasks in integrated circuit (IC) design. As Moore's law continues to hold sway, more and more devices and circuits can be packed on a single chip. In the meantime, the silicon chip size also grows to accommodate the capability of multi-system integration. Furthermore, the required supply voltage is progressively reduced from one generation to another in order to save power. One conventional power mesh method (described in U.S. Pat. No. 6,480,989 incorporated herein by reference) to form a power supply distribution network begins to face a tremendous challenge. It can no longer guarantee a predetermined voltage level at all comers of the chip. In other words, the inevitable I*R voltage drop on the supply is known to cause problems, such as slew rate, duty cycle, jitter, timing, etc. to be out of control. This impact has caused both high-speed analog and digital circuits to miss their performance targets and fail the specification. One possible solution is to use low Vt devices to gain back some over-drivability; however, this is achieved at a cost of high power consumption which is undesirable.
Therefore, a more intelligent power distribution network is urgently needed for today's very large scale IC chips or chip complexes. The concept of programmable power distribution network has never been proposed on the semiconductor chip, but only on utility service provided for residences and commercial buildings (U.S. Pat. No. 6,341,054). One possible reason that this concept has not been implemented on the chip is lack of an efficient switch means which can easily be integrated with an IC chip to do the job. There are many disadvantages of using semiconductor devices, either MOS or bipolar, for power switching. The device has certain on state resistance, and off state leakage. One example to use such a switch to detect and isolate the shorts on the supply of a chip has been proposed and described (U.S. Pat. No. 6,320,400).
Some techniques regarding the design of a power distribution network to reduce delta-I noise or increase electro-migration resistance can be found in the following patent (U.S. Pat. No. 5,694,329, U.S. Pat. No. 6,483,435, U.S. Pat. No. 6,335,494, U.S. Pat. No. 6,061,609). So far, none of them has mentioned to use MEMS for designing a robust on-chip power distribution network.
On the other hand, MEM switch development and on-chip integration schemes have become more and more mature. These can be found in the following US patent references:    1. Method for constructing an encapsulated MEMS band-pass filter for integrated circuits—U.S. Pat. No. 6,429,755    2. Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof—U.S. Pat. No. 6,399,406    3. Capacitive microelectromechanical switches—U.S. Pat. No. 6,394,942    4. Low actuation voltage microelectromechanical device and method of manufacture—U.S. Pat. No. 6,143,997    5. Micro electromechanical RF switch—U.S. Pat. No. 5,578,976    6. Capacitive Microelectromechanical Switches—U.S. Pat. No. 6,452,124.However, where MEMS have been used, such switches have been used for signal propagation, not in applications involving power to the chips.